FIG. 8 is a schematic block diagram showing processes for processing the data according to the fourth embodiment of the present disclosure. As compared with FIG. 3, in FIG. 8, the five processes 301?305 are unchanged, but two processes of repetition 311 and bit permutation 312 are newly added between the process of rate matching 303 and the process of modulation 304. Specifically, as shown in FIG. 8, it is assumed that a bit sequence of b1, b2, . . . , bm is obtained after the process of rate matching 303, and these m bits b1, b2, . . . , bm are repeated into m*M bits b1, b2, . . . , bm*M in the process of repetition 311. Then, these m*M bits are further performed the processing of bit permutation in the process of bit permutation 312 which is similar with the process of bit permutation 310 in the second embodiment. That is, in the process of bit permutation 312, different bit permutation patterns are used according to different repetition levels. Subsequently, these m*M bits after bit permutation are further subject to the processes 304 and 305 and finally mapped onto M subframes. FIG. 9 shows a typical example of the processes 311 and 312.
