In one embodiment, the controller 202 includes a microcontroller, the nonvolatile memory 205 includes a Flash Memory, the volatile memory 206 includes a Static Random Access Memory Integrated Circuit (SRAM IC), the communication element 207 includes a Bluetooth System On Chip (SoC), the camera 203 includes a complementary metal oxide semiconductor (CMOS) camera, the dataflow manager 204 includes a Complex Programmable Logic Device (CPLD), the scale 116 can include a strain gauge or a force-sensitive resistor (FSR), etc., and the power source 201 includes a rechargeable battery, e.g., a Lithium-Polymer battery. The circuit 106 can implement a system-on-board designed to manage, process and/or analyze data produced by the image sensor. A customized memory controller can be implemented in the CPLD. The CPLD coordinates high speed data movement between the image sensor and the storage buffer.

In the multi-layer board configuration, the bottle facing layer can include the camera 203, controller 202, dataflow manager 204, volatile memory 206, and non-volatile memory 205. The cap facing layer can include the communication element 207, power source 201, and peripheral circuit elements, e.g., voltage regulators. An interface between the two layers a, b in the form of a connector, e.g., a 12 pin connector, electrically connects the two layers a, b, to allow for the transmission of data and power, etc. between the two layers a, b. The layers can utilize both sides of the PCBs for components.