The substrate 201 may serve as a base of the memory cell 200. In one embodiment, the substrate includes a surface crystalline layer 205 separated from a bulk crystalline layer 203 by an insulator layer 207. The substrate 201, for example, is a crystalline-on-insulator (COI) substrate. The COI substrate may be a silicon-on-insulator (SOI) substrate. Other suitable types of COI substrates, such as germanium-on-insulator (GeOI) substrate, may also be useful. As for the insulator layer, it may be formed of a dielectric material. The insulator layer, for example, includes silicon oxide, which provides a buried oxide (BOX) layer 207. Other types of dielectric materials may also be useful. It is understood that the surface and bulk crystalline layers need not be formed of the same material. The surface crystalline layer 205 may be referred to as the body substrate and the bulk crystalline layer 203 may be referred to as the base substrate.

The substrate 201, in one embodiment, employs a very thin body substrate 205 and a very thin BOX layer 207. For example, the body substrate 205 is a very thin silicon body. In one embodiment, the thickness of the body substrate is about 5-10 nm, while the thickness of the BOX layer is about 10-30 nm. This forms an ultra-thin body SOI substrate, such as a fully depleted SOI (FDSOI) substrate. Providing an ultra-thin body SOI substrate enables better control of a transistor channel region 214, which will be described in greater detail later. Other suitable thickness dimensions for the body substrate and BOX layer may also be useful as long as they are sufficiently thin to provide improved control of the transistor channel region.