In another embodiment, a non-volatile MTP memory cell is disclosed. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. The SOI substrate includes a very thin buried oxide (BOX) layer disposed between a base substrate and a very thin body substrate layer. The memory cell includes a transistor having a floating gate disposed on the SOI substrate. The transistor includes first and second source/drain (S/D) regions disposed in the body substrate layer and adjacent to sides of the floating gate. The memory cell includes a control capacitor having a control gate disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and control gate. A first portion of the device well defines a capacitor back-gate embedded within the base substrate. First and second doped regions are disposed between the control gate and capacitor back-gate. The capacitor back-gate is in electrical communication with the control gate. A contact region disposed within the device well.