A device well 240 may be provided within the cell region 284. For example, the device well is disposed within the base substrate 203. In one embodiment, the device well includes first polarity type dopants. The first polarity type may be the same polarity type as the capacitor polarity type. For example, the device well is doped with n-type dopants for a n-type capacitor. The dopant concentration of the device well is, for example, about 1E10-1E12 cm^?2. Other dopant concentrations may also be useful. As shown, the device well 240 includes a depth deeper than the isolation region 280. The device well, for example, extends below the isolation region 280 and traverses the active capacitor and active transistor regions to underlap the storage and control gates 236 and 256. The device well may form back-gates embedded in the base substrate 203 within the active regions of the cell region 284. In one embodiment, the device well 240 forms a back-gate of the capacitor 130 and the transistor 150. For example, a capacitor back-gate may be defined by the portion of device well which traverses the active capacitor region 220 and underlaps the second doped region 218, while a transistor back-gate may be defined by the portion of device well which traverses the active transistor region 222, and underlaps the channel region 214.