Although one back contact region 224 is illustrated for a device well 240, it is understood that each row of memory cells may also be provided with multiple back contact regions disposed in the device well, depending on design requirements.

As shown, the memory cells are interconnected to form two columns connected by BLs (BL0 and BL1) and SLs (SL0 and SL1) and two rows of memory cells connected by CGLs (CGL0 and CGL1). In one embodiment, the SLs (SL0 and SL1) of each column of memory cells are coupled to separate source terminals. For example, SL0 and SL1 are coupled to first and second source terminals and BL0 and BL1 are coupled to first and second bitline terminals. In one embodiment, the CGL of each row of memory cells is commonly coupled to the control contact region and back contact region of the device well. For example, a control terminal of a CGL provides a common bias to the control gate and capacitor back-gate of the row of memory cells.

Although a 2×2 portion of an array is shown, it is understood that the array may include numerous rows and columns. For example, the memory array may form a memory block. The memory array may also include other suitable types of array configurations.