Referring to FIG. 5i, a portion of the body substrate 205 and BOX layer 203 is removed to form a trench region 290 above a portion of the base substrate. For example, the trench region extends to a sufficient depth to expose a back contact region 224 disposed within the base substrate so that a back contact can be formed for biasing the capacitor back-gate. Mask and etch techniques may be employed to form the trench region 290. For example, a patterned etch mask and a suitable etchant may be employed to selectively remove an exposed portion of the epitaxial layer 432, body substrate 205 and BOX layer 207 to form the trench 290 for a back contact as shown.

The process continues to complete forming the device. The process may include forming a silicide block 261 over the storage and control gates. The silicide block, for example, is a dielectric material, such as silicon oxide or silicon nitride. Other types of silicide block materials may also be useful. Providing a silicide block over the storage and control gates prevents formation of silicide contacts over these gates. Metal silicide contacts (not shown) may be provided on contact regions of the memory cell. For example, metal silicide contacts are provided on the raised S/D regions 232r and 234r, raised control contact region 252r, and the back contact region. The metal silicide contacts may be formed by any suitable techniques.

The processing may continue to form an interlayer dielectric (ILD) layer, conductive contact plugs coupled to the terminals of the memory cell, conductive contacts as well as one or more interconnect levels, final passivation, dicing, assembly and packaging. Other processes to complete forming the memory device may also be included.