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MTP memory for SOI process

專利號(hào)
US10096602B1
公開日期
2018-10-09
申請(qǐng)人
GLOBALFOUNDRIES Singapore Pte. Ltd.(SG Singapore)
發(fā)明人
Shyue Seng Jason Tan; Kiok Boone Elgin Quek
IPC分類
H01L27/06; H01L27/105; H01L29/423; H01L29/788; H01L27/12; H01L29/78; H01L29/66; H01L21/84
技術(shù)領(lǐng)域
gate,region,capacitor,substrate,doped,regions,transistor,dopants,cell,memory
地域: Singapore

摘要

Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

說明書

In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of various embodiments. In the following description, various embodiments of the present disclosure are described with reference to the following, in which:

FIG. 1 shows a schematic diagram of an embodiment of a memory cell;

FIG. 2a shows a top view of an embodiment of a memory cell and FIGS. 2b-2d show various cross-sectional views of an embodiment of the memory cell;

FIG. 3 shows a schematic diagram of an embodiment of a memory array;

FIGS. 4a-4b show various operations of an embodiment of a memory cell; and

FIGS. 5a-5i show cross-sectional views of an embodiment of a process for forming a memory cell.

DETAILED DESCRIPTION

權(quán)利要求

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