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Semiconductor devices including a dummy gate structure on a fin

專利號(hào)
US10096605B2
公開日期
2018-10-09
申請(qǐng)人
Samsung Electronics Co., Ltd.（KR）
發(fā)明人
Sang-Jine Park; Kee-Sang Kwon; Do-Hyoung Kim; Bo-Un Yoon; Keun-Hee Bai; Kwang-Yong Yang; Kyoung-Hwan Yeo; Yong-Ho Jeon
IPC分類
H01L29/06; H01L27/11; H01L27/088; H01L21/8234; H01L29/78; H01L27/092; H01L29/08; H01L29/16; H01L29/161; H01L29/165; H01L21/762
技術(shù)領(lǐng)域
layer,gate,141b,dummy,first,insulation,spacer,may,recess,fins
地域： Suwon-si, Gyeonggi-do

摘要

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

說明書

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of and claims priority from U.S. patent application Ser. No. 15/371,751, filed on Dec. 7, 2016, which is a continuation of and claims priority from U.S. patent application Ser. No. 15/047,181, filed on Feb. 18, 2016, now U.S. Pat. No. 9,548,309, which is a continuation application of and claims priority from U.S. patent application Ser. No. 14/639,494, filed on Mar. 5, 2015, now U.S. Pat. No. 9,299,700, which claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2014-0054924, filed on May 8, 2014 in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated herein by reference in their entireties.

BACKGROUND

The present disclosure relates to semiconductor devices. As one example of scaling techniques for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed, in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and a gate is then formed on a surface of the silicon body. Because the multi-gate transistor uses a three-dimensional (3D) channel, scaling of the multi-gate transistor may be relatively easily achieved. In addition, current controlling capability can be improved even without increasing a gate length of the multi-gate transistor. Further, a short channel effect (SCE), in which an electric potential of a channel region is affected by a drain voltage, can be reduced.

SUMMARY

權(quán)利要求

1
What is claimed is:1. A semiconductor device comprising:a substrate;a fin protruding from the substrate and extending in a first direction;a recess in the fin and extending in a second direction that is substantially perpendicular to the first direction;a first gate structure crossing over the fin on a first side of the recess;a second gate structure crossing over the fin on a second side of the recess;a first source/drain region between the first gate structure and the recess; anda second source/drain region between the second gate structure and the recess,wherein the recess includes a portion in which a width increases as a depth of the recess in the fin increases.2. The semiconductor device of claim 1, wherein a widest width of the recess is at a bottom portion of the recess.3. The semiconductor device of claim 2, wherein the bottom portion of the recess is lower than a bottom portion of the first source/drain region in a depth direction.4. The semiconductor device of claim 1, wherein a first width of the recess at a level corresponding to a bottom portion of the first source/drain region is smaller than a second width of the recess at a bottom portion of the recess.5. The semiconductor device of claim 1,wherein a first width of the recess adjacent a top surface of the fin is smaller than a second width of the recess at a level corresponding to a bottom portion of the first source/drain region, andwherein a third width of the recess at a bottom portion of the recess is greater than the second width.6. The semiconductor device of claim 1, wherein a height of the recess is smaller than that of the fin.7. The semiconductor device of claim 1, further comprising a device isolation layer in the recess.8. The semiconductor device of claim 7, further comprising a capping layer that conforms to an inner surface of the recess, wherein the device isolation layer is on the capping layer.9. The semiconductor device of claim 1, further comprising a dummy gate structure crossing over the recess.10. The semiconductor device of claim 9, further comprising first and second spacers at opposite sides of the dummy gate structure.11. The semiconductor device of claim 10,wherein the dummy gate structure includes a gate electrode and a gate insulation layer, andwherein a widest width of the recess is wider than a widest width of the dummy gate structure.12. The semiconductor device of claim 1,wherein the first gate structure comprises a first gate electrode on a first gate insulation layer, andwherein the second gate structure comprises a second gate electrode on a second gate insulation layer.13. A semiconductor device comprising:a fin protruding from a substrate and extending in a first direction;a recess extending in a second direction different from the first direction in the fin;a dummy gate structure overlapping the recess extending in the second direction;a spacer on a sidewall of the dummy gate structure on the fin;an inner spacer on an inner sidewall of the spacer; anda source/drain region at opposite sides of the recess,wherein a lowermost portion of the recess comprises a first portion,wherein the recess further comprises a second portion above the first portion, andwherein a width of the second portion in the first direction is smaller than a width of the first portion in the first direction.14. The semiconductor device of claim 13, wherein the second portion is coplanar with a lowermost portion of the source/drain region.15. The semiconductor device of claim 14, wherein the recess comprises a sidewall extending vertically from an upper surface of the substrate to the second portion.16. The semiconductor device of claim 14,wherein the recess comprises a third portion between the first portion and the second portion, andwherein a width of the third portion in the first direction is smaller than the width of the first portion in the first direction, and is greater than the width of the second portion in the first direction.
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