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Semiconductor devices including a dummy gate structure on a fin

專利號(hào)
US10096605B2
公開日期
2018-10-09
申請(qǐng)人
Samsung Electronics Co., Ltd.(KR)
發(fā)明人
Sang-Jine Park; Kee-Sang Kwon; Do-Hyoung Kim; Bo-Un Yoon; Keun-Hee Bai; Kwang-Yong Yang; Kyoung-Hwan Yeo; Yong-Ho Jeon
IPC分類
H01L29/06; H01L27/11; H01L27/088; H01L21/8234; H01L29/78; H01L27/092; H01L29/08; H01L29/16; H01L29/161; H01L29/165; H01L21/762
技術(shù)領(lǐng)域
layer,gate,141b,dummy,first,insulation,spacer,may,recess,fins
地域: Suwon-si, Gyeonggi-do

摘要

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

說明書

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a “first” element could be termed a “second” element without departing from the teachings of the present embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As appreciated by the present inventive entity, devices and methods of forming devices according to various embodiments described herein may be embodied in microelectronic devices such as integrated circuits, wherein a plurality of devices according to various embodiments described herein are integrated in the same microelectronic device. Accordingly, the cross-sectional view(s) illustrated herein may be replicated in two different directions, which need not be orthogonal, in the microelectronic device. Thus, a plan view of the microelectronic device that embodies devices according to various embodiments described herein may include a plurality of the devices in an array and/or in a two-dimensional pattern that is based on the functionality of the microelectronic device.

權(quán)利要求

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