Semiconductor devices including a dummy gate structure on a fin
摘要
說(shuō)明書
The device isolation layer 143 may fill the recess 141b. Therefore, the device isolation layer 143 may extend in the second direction Y1. The device isolation layer 143 may be formed on the field insulation layer 110 and may be formed in the first to third fins F1 to F3. Since the device isolation layer 143 fills the recess 141b, a bottom surface of the device isolation layer 143 is lower than bottom surfaces of first to third source/drain regions 121, 123 and 125. The device isolation layer 143 may isolate source/drain regions 123 formed at opposite sides of the device isolation layer 143 to inhibit/prevent a short from occurring and to inhibit/prevent current from flowing. The device isolation layer 143 may include, for example, an oxide layer, a nitride layer, or an oxynitride layer. The device isolation layer 143 is spaced apart from the first to third source/drain regions 121, 123 and 125.
Top surfaces of the first and second gate structures 151a and 151b may be coplanarly positioned with a top surface of the dummy gate structure 152.
The first and second gate structures 151a and 151b may include respective first and second gate insulation layers 153a and 153b and respective first and second gate electrodes 155a and 155b.
