Semiconductor devices including a dummy gate structure on a fin
摘要
說明書
The first to third source/drain regions 121, 123 and 125 may be elevated source/drain regions. Therefore, top surfaces of the first to third source/drain regions 121, 123 and 125 may be higher than top surfaces of the first to third fins F1 to F3.
When the semiconductor device 1 is a PMOS transistor, the first to third source/drain regions 121, 123 and 125 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than silicon (Si), such as, for example, SiGe. The compressive stress material may improve the mobility of carriers of a channel region by applying compressive stress to the first to third fins F1 to F3 under the first and second gate structures 151a and 151b, that is, the channel region.
When the semiconductor device 1 is an NMOS transistor, the first to third source/drain regions 121, 123 and 125 may include the same material as the substrate 101 or a tensile stress material. For example, when the substrate 101 includes Si, the first to third source/drain regions 121, 123 and 125 may include Si or a material having a smaller lattice constant than Si (e.g., SiC or Silicon Phosphide (SiP)).
The first to third source/drain regions 121, 123 and 125 may be formed through epitaxial growth.
