Semiconductor devices including a dummy gate structure on a fin
摘要
說明書
The inner spacer 170 is formed on inner sidewalls of the spacers 116 and 117. In detail, the inner spacer 170 is formed on sidewalls of the first region 116a and the third region 117a. A height of the inner spacer 170 may be equal to heights of the first and third regions 116a and 117a. A profile of the inner spacer 170 and a profile of the recess 141b may be connected. The inner spacer 170 may include, for example, at least one of an oxide layer, a nitride layer and an oxynitride layer.
The capping layer 142 may be formed between the recess 141b and the device isolation layer 143. The capping layer 142 may be conformally formed along an inner surface of the recess 141b. In addition, the capping layer 142 may extend to be conformally formed along the sidewalls of the spacers 116 and 117. The capping layer 142 may be disposed between each of the spacers 116 and 117 and the dummy gate structure 152. The capping layer 142 may include, for example, at least one of an oxide layer, a nitride layer and an oxynitride layer.
The dummy gate structure 152 is formed on the device isolation layer 142. A bottom surface of the dummy gate structure 152 may be higher than bottom surfaces of the first and second gate structures 151a and 151b. In other words, a top surface of the device isolation layer 143 may be higher than or at the same level with top surfaces of the first to third fins F1 to F3.
