Semiconductor devices including a dummy gate structure on a fin
摘要
說明書
When the bottom surface of the dummy gate structure 152 is higher than the bottom surfaces of the first and third regions 116a and 117a, the device isolation layer 143 may have fifth to seventh regions 143a, 143b and 143c. Here, the fifth region 143a of the device isolation layer 143 is a region filling the recess 141b, the sixth region 143b is a region between the first and third regions 116a and 117a disposed on the fifth region 143a, and the seventh region 143c is a region extending from the sixth region 143b to the bottom surface of the dummy gate structure 152. A width of the seventh region 143c is greater than or equal to a width of the sixth region 143b. Therefore, a portion of the first region 116a and a portion of the third region 117a may be disposed between the seventh region 143c and each of the first to third fins F1 to F3. In addition, the first region 116a and the third region 117a may cover a portion of the bottom surface of the dummy gate structure 152. In other words, the portion of the first region 116a and the portion of the third region 117a may be disposed between each of the first to third fins F1 to F3 and the dummy gate structure 152, but aspects of present inventive concepts are not limited thereto. The bottom surface of the dummy gate structure 152 may come into contact with the seventh region 143c.
