The dummy gate structure 152 may include the dummy gate insulation layer 153c, the barrier layer 154, and the dummy gate electrode 155c, and the dummy gate electrode 155c may include first and second metal layers MG1 and MG2.
The dummy gate insulation layer 153c is disposed on the sidewalls of the spacer 115 but is not disposed in the recess 141b. The dummy gate insulation layer 153c may have an L shape. The barrier layer 154 is disposed on the dummy gate insulation layer 153c but is not disposed on the recess 141b. A width of the recess 141b is wider than a width of the first spacer 115.
The dummy gate electrode 155c fills the recess 141b and is formed on the recess 141b. For example, the recess 141b may be filled with the first metal layer MG1, and the second metal layer MG2 may be formed on the first metal layer MG1.
Hereinafter, a semiconductor device 6 according to some embodiments of present inventive concepts will be described with reference to