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Semiconductor devices including a dummy gate structure on a fin

專利號
US10096605B2
公開日期
2018-10-09
申請人
Samsung Electronics Co., Ltd.(KR)
發(fā)明人
Sang-Jine Park; Kee-Sang Kwon; Do-Hyoung Kim; Bo-Un Yoon; Keun-Hee Bai; Kwang-Yong Yang; Kyoung-Hwan Yeo; Yong-Ho Jeon
IPC分類
H01L29/06; H01L27/11; H01L27/088; H01L21/8234; H01L29/78; H01L27/092; H01L29/08; H01L29/16; H01L29/161; H01L29/165; H01L21/762
技術領域
layer,gate,141b,dummy,first,insulation,spacer,may,recess,fins
地域: Suwon-si, Gyeonggi-do

摘要

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

說明書

Next, a semiconductor device 8 according to some embodiments of present inventive concepts will be described with reference to FIGS. 14 to 16. In the semiconductor device 8, repeated descriptions of the same content as described above may be omitted, and the following description will focus on differences.

FIG. 14 is a perspective view of a semiconductor device 8 according to some embodiments of present inventive concepts, FIG. 15 is a cross-sectional view taken along the line A-A of FIG. 14, and FIG. 16 is a cross-sectional view taken along the line B-B of FIG. 14. The first and second interlayer insulation layers 131 and 132 may be provided in the semiconductor device 8, even if they are not explicitly illustrated in FIG. 14.

Unlike in the semiconductor device 1 shown in FIG. 1, in the semiconductor device 8 shown in FIG. 14, a dummy gate structure 152 is not formed. Instead, a device isolation layer 175 may fill a region that might otherwise be filled with the dummy gate structure 152.

權利要求

1
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