Semiconductor devices including a dummy gate structure on a fin
摘要
說明書
In detail, referring to
The device isolation layer 175 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, lanthanum oxide, polysilicon, germanium, germanium oxide, titanium oxide, and tungsten oxide.
A capping layer 173 may be formed between the recess 141b and the device isolation layer 175. The capping layer 173 may be conformally formed along sidewalls of a first spacer 115, top surfaces of the first to third fins F1 to F3, and an inner surface of the recess 141b. The capping layer 173 may be disposed on the first to third fins F1 to F3 and a field insulation layer 110.
The capping layer 173 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, Hf oxide, La oxide, polysilicon, Ge, Ge oxide, Ti oxide, and W oxide.
Meanwhile, a second capping layer (e.g., the second capping layer 174 illustrated in
