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Semiconductor devices including a dummy gate structure on a fin

專利號
US10096605B2
公開日期
2018-10-09
申請人
Samsung Electronics Co., Ltd.（KR）
發(fā)明人
Sang-Jine Park; Kee-Sang Kwon; Do-Hyoung Kim; Bo-Un Yoon; Keun-Hee Bai; Kwang-Yong Yang; Kyoung-Hwan Yeo; Yong-Ho Jeon
IPC分類
H01L29/06; H01L27/11; H01L27/088; H01L21/8234; H01L29/78; H01L27/092; H01L29/08; H01L29/16; H01L29/161; H01L29/165; H01L21/762
技術(shù)領(lǐng)域
layer,gate,141b,dummy,first,insulation,spacer,may,recess,fins
地域： Suwon-si, Gyeonggi-do

摘要

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

說明書

The dummy gate insulation layer 153c may be formed between each of the first to third fins F1 to F3 and the dummy gate electrode 155c. The dummy gate insulation layer 153c may be formed along the top surface of the device isolation layer 143 and the sidewalls of the first spacer 115. The dummy gate insulation layer 153c may include a high-k material having a higher dielectric constant than a silicon oxide layer. For example, the dummy gate insulation layer 153c may include HfO2, ZrO2, LaO, Al2O3 or Ta2O5.

The dummy gate electrode 155c may include first and second metal layers MG1 and MG2. In some embodiments, the dummy gate electrode 155c may include two or more sequentially stacked metal layers MG1 and MG2. For example, the first metal layer MG1 may include at least one of TiN, TaN, TiC, TiAlC and TaC. In addition, the second metal layer MG2 may include W or Al. In some embodiments, the dummy gate electrode 155c may include a non-metal material, e.g., Si or SiGe.

Referring to FIG. 50, the protection layer 133 disposed on the first interlayer insulation layer 131 is removed. To remove the protection layer 133, a planarization process may be performed. Therefore, the first and second gate structures 151a and 151b and the dummy gate structure 152 may also be partially removed.

權(quán)利要求

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