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Modified tungsten silicon

專利號
US10096609B2
公開日期
2018-10-09
申請人
GLOBALFOUNDRIES INC.（KY Grand Cayman）
發(fā)明人
Nicolas L. Breil; Domingo A. Ferrer; Keith Kwong Hon Wong
IPC分類
H01L23/525; H01L27/112; H01L23/522; H01L23/532; H01L21/768
技術(shù)領(lǐng)域
tungsten,mx,silicon,tetragonal,layer,conductive,may,fuse,deposition,be
地域： Grand Cayman

摘要

A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.

說明書

1 2 3 4 5 6 7 8 9 10 11
BACKGROUND

The present invention relates to semiconductor devices, and particularly to forming e-fuse and precision resistor structures.

Many integrated circuits (“ICs”) are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. It is generally desirable that ICs operate as fast as possible, and consume as little power as possible. Semiconductor ICs often include one or more types of memory, such as CMOS memory, antifuse memory, and efuse memory.

One-time-programmable (“OTP”) memory elements are used in ICs to provide non-volatile memory (“NVM”). Data in NVM are not lost when the IC is turned off. NVM allows an IC manufacturer to store lot number and security data on the IC, for example, and is useful in many other applications. One type of NVM is commonly called an E-fuse.

E-fuses are usually integrated into semiconductor ICs by using a stripe (commonly also called a “l(fā)ink”) of conducting material (metal, poly-silicon, etc.) between two pads, generally referred to as anode and cathode. Applying a fuse current (IFUSE) to the E-fuse destroys the link, thus changing the resistance of the E-fuse. This is commonly referred to as “programming” the E-fuse. The fuse state (i.e., whether it has been programmed) can be read using a sense circuit, which is common in the art of electronic memories.

BRIEF SUMMARY

權(quán)利要求

1
What is claimed is:1. A method of forming a semiconductor structure, the method comprising:forming a single amorphous tungsten silicon layer directly on an insulator, wherein the single amorphous tungsten silicon layer comprises tungsten and silicon, and wherein the single amorphous tungsten silicon layer has a substantially amorphous structure;converting the single amorphous tungsten silicon layer to a tetragonal phase tungsten silicon layer by performing a laser spike anneal of the single amorphous tungsten silicon layer, wherein the tetragonal phase tungsten silicon layer has a tetragonal crystalline structure, and wherein the converting the single amorphous tungsten silicon layer to the tetragonal phase tungsten silicon layer includes reducing a resistance of the single amorphous tungsten silicon layer; andafter converting the single amorphous tungsten silicon layer to a tetragonal phase tungsten silicon layer, forming a first conductive material and a second conductive material on the tetragonal phase tungsten silicon layer, wherein the tetragonal phase tungsten silicon layer forms an electrical connection between the first conductive material and the second conductive material, andwherein the tetragonal phase tungsten silicon layer directly contacts the first conductive material and wherein the tetragonal phase tungsten silicon layer directly contacts the second conductive material.2. The method of claim 1, wherein the single amorphous tungsten silicon layer has a molar ratio of silicon to tungsten in the range of about 2.2 to about 3.0.3. The method of claim 1, wherein the single amorphous tungsten silicon layer has a molar ratio of silicon to tungsten in the range of about 2.6 to about 2.8.4. The method of claim 1, wherein the single amorphous tungsten silicon layer has a molar ratio of silicon to tungsten of about 2.7.5. The method of claim 1, wherein the laser spike anneal is performed at a temperature ranging from about 900 to about 1150° C.6. The method of claim 1, wherein converting the single amorphous tungsten silicon layer to a tetragonal phase tungsten silicon layer comprises causing a reduction in a temperature coefficient of resistance of the single amorphous tungsten silicon layer.7. The method of claim 1, wherein the laser spike anneal is performed for a time period ranging from approximately 0.1 milliseconds to approximately 10 milliseconds.8. The method of claim 1, wherein the causing the reduction in the resistance of the single amorphous tungsten silicon layer includes decreasing the resistance of the single amorphous tungsten silicon layer by approximately at least 5%.9. The method of claim 1, wherein the causing the reduction in the resistance of the single amorphous tungsten silicon layer includes decreasing the resistance of the single amorphous tungsten silicon layer by approximately over 50%.10. The method of claim 1, wherein a thickness of the tetragonal phase tungsten silicon layer is approximately 10 nanometers (nm) to approximately 20 nm.11. The method of claim 1, wherein the tetragonal phase tungsten silicon layer, the first conductive material, and the second conductive material form a precision resistor.12. A method of forming a semiconductor structure, the method comprising:forming a single tungsten silicon layer directly on an insulator, wherein the single tungsten silicon layer comprises tungsten and silicon;performing a laser spike anneal at a temperature ranging from about 900 to about 1150° C. on the single tungsten silicon layer to cause a reduction in resistance of the tungsten silicon layer; andforming an e-fuse structure including the single tungsten silicon layer.13. The method of claim 12, wherein the single tungsten silicon layer has a molar ratio of silicon to tungsten in the range of about 2.2 to about 3.0.14. The method of claim 12, wherein the single tungsten silicon layer has a molar ratio of silicon to tungsten in the range of about 2.6 to about 2.8.15. The method of claim 12, wherein the single tungsten silicon layer has a substantially amorphous structure or a hexagonal structure.16. The method of claim 12, wherein performing the laser spike anneal comprises converting a crystalline structure of the single tungsten silicon layer to a tetragonal crystalline structure.17. The method of claim 12, wherein performing the laser spike anneal comprises causing a reduction in a temperature coefficient of resistance of the single tungsten silicon layer.18. The method of claim 12, wherein the forming the efuse structure includes, after performing the laser spike anneal, forming a first conductive material and a second conductive material on the single tungsten silicon layer, wherein the single tungsten silicon layer forms an electrical connection between the first conductive material and the second conductive material.
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