Circuit structure, transistor and semiconductor device
地域：
Hsin-Chu
摘要
A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a AlxGa(1-X)N (AlGaN) layer over the III-V semiconductor compound, a gate over the AlGaN layer, a passivation film over the gate and over a portion of the AlGaN layer, a source structure, and a drain structure on an opposite side of the gate from the source structure, wherein X ranges from 0.1 to 1. The source structure has a source contact portion and an overhead portion. The overhead portion is over at least a portion of the passivation film between the source contact portion and the gate. A distance between the source contact portion and the gate is less than a distance between the gate and the drain structure.
說明書
The present application is a continuation of U.S. application Ser. No. 14/827,839 issuing as U.S. Pat. No. 9,553,182, which is a divisional of U.S. application Ser. No. 13/650,548, filed Oct. 12, 2012, which claims priority of U.S. Provisional Application No. 61/564,614, filed Nov. 29, 2011, which are all incorporated herein by reference in their entireties.
This disclosure relates generally to semiconductor circuit manufacturing processes and, more particularly, to a group-III group-V (III-V) compound semiconductor based transistor.
Group-III group-V compound semiconductors (often referred to as III-V compound semiconductors), such as gallium nitride (GaN) and its related alloys, have been under intense research in recent years due to their promising applications in electronic and optoelectronic devices. The large band gap and high electron saturation velocity of many III-V compound semiconductors make them excellent candidates for applications in high temperature, high voltage, and high-speed power electronics. Particular examples of potential electronic devices employing III-V compound semiconductors include high electron mobility transistors (HEMTs) and other heterojunction transistors.
權(quán)利要求
What is claimed is:1. A method comprising:epitaxially growing a semiconductor layer over a silicon substrate; epitaxially growing a donor-supply layer over the semiconductor layer; forming a gate on the donor-supply layer; depositing a dielectric layer over the gate and the donor-supply layer; etching a portion of the dielectric layer to form a first opening and a second opening each of the first opening and the second opening exposing a portion of the donor-supply layer, wherein the first opening and the second opening are disposed on opposite sides of the gate; depositing one or more metal layers over the first opening, the second opening, and the dielectric layer; and etching a portion of the one or more metal layers to remove the one or more metal layers from a region of a top surface of the dielectric layer between the gate and the second opening thereby forming a source structure and a drain structure, wherein after the etching, the source structure comprises a source overhead portion disposed over at least a portion of the dielectric layer between the source structure and the gate. 2. The method of claim 1 , wherein the depositing the one or more metal layers comprises:depositing a first metal layer including titanium; and depositing a second metal layer including aluminum over the first metal layer. 3. The method of claim 2 , wherein the depositing the one or more metal layers further comprises depositing a third metal layer over the second metal layer. 4. The method of claim 3 , wherein the third metal layer includes nickel, copper, titanium, or titanium nitride. 5. The method of claim 1 , wherein depositing the dielectric layer comprises depositing a silicon nitride film using plasma enhanced chemical vapor deposition (PECVD), depositing a silicon nitride film using low pressure chemical vapor deposition (LPCVD), or depositing a silicon oxide film using PECVD. 6. The method of claim 1 , wherein the dielectric layer is at least one of silicon nitride, silicon oxide, silicon oxynitride, carbon doped silicon oxide, carbon doped silicon nitride, carbon doped silicon oxynitrides, zinc oxide, zirconium oxide, hafnium oxide or titanium oxide. 7. The method of claim 1 , wherein etching the portion of the one or more metal layers forms the source overhead portion overlapping at least the portion of the gate. 8. The method of claim 1 , wherein the source overhead portion overlaps a portion of the dielectric layer over a drift region between the gate and the drain structure. 9. A method comprising:epitaxially growing a first semiconductor layer over a substrate; epitaxially growing a second semiconductor layer over the first semiconductor layer; forming a gate on the second semiconductor layer; depositing a passivation film over the gate and the first and second semiconductor layers; etching a first opening and a second opening in the passivation film, wherein the etching exposes the second semiconductor layer, and wherein the first opening and the second opening are disposed on opposite sides of the gate; depositing ohmic metal layers over the passivation film and in the first and second openings; and etching a portion of the ohmic metal layers to form a source structure and a drain structure, wherein the source structure comprises:a first portion disposed over the first opening; and a second portion extending over at least a portion of the passivation film between the first portion and the gate, wherein the second portion overlies at least a portion of the gate. 10. The method of claim 9 , wherein etching the portion of the ohmic metal layers forms the second portion also overlying a portion of the passivation film in a drift region between the gate and the drain structure in the second opening. 11. The method of claim 9 , wherein depositing the passivation film comprises depositing a silicon nitride film using plasma enhanced chemical vapor deposition (PECVD), depositing a silicon nitride film using low pressure chemical vapor deposition (LPCVD), or depositing a silicon oxide film using PECVD. 12. The method of claim 9 , wherein etching the portion of the ohmic metal layers forms the drain structure comprising:a drain contact portion disposed in the second opening; and a drain overhead portion disposed over at least a portion of the passivation film between the drain structure and the gate. 13. The method of claim 9 , wherein the depositing the ohmic metal layers and etching the ohmic layers forms the second portion of the source structure directly on the passivation film. 14. A method comprising:epitaxially growing a semiconductor layer over a substrate; epitaxially growing a donor-supply layer over the semiconductor layer; forming a gate over the donor-supply layer; forming a passivation layer over the gate, wherein the passivation layer has a first opening on a first side of the gate and a second opening on a second side of the gate opposite the first side of the gate; conformally depositing one or more metal layers over the first opening, the second opening, and the passivation layer; and etching the one or more metal layers to form a third opening in the one or more metal layers, wherein the third opening exposes the passivation layer and is disposed between the gate and the second opening of the passivation layer, wherein after the etching the one or more metal layers contiguously extend from the first opening to a first distance on the second side of the gate. 15. The method of claim 14 , further comprising:forming a channel between the semiconductor layer and the donor-supply layer. 16. The method of claim 14 , wherein the etching the one or more metal layers to form the third opening includes:forming an etch mask over the first opening and the second opening; and plasma etching the third opening while the etch mask is over the first and second openings. 17. The method of claim 14 , wherein etching the one or more metal layers includes etching a plurality of metals in a same chamber. 18. The method of claim 14 , wherein etching the one or more metal layers includes an inductively coupled plasma (ICP) etch using at least one of a fluorine-based etchant, a bromine-based etchant, or a chlorine-based etchant. 19. The method of claim 14 , further comprising:after the etching, annealing the substrate including the etched one or more metal layers. 20. The method of claim 14 , wherein the forming the passivation layer includes depositing a dielectric material and etching the first opening and the second opening in the dielectric material to expose the donor-supply layer.
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