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Field effect transistors having a fin

專(zhuān)利號(hào)
US10096696B2
公開(kāi)日期
2018-10-09
申請(qǐng)人
MICRON TECHNOLOGY, INC.（US ID Boise）
發(fā)明人
Toru Tanzawa
IPC分類(lèi)
H01L27/00; H01L29/66; H01L29/78; H01L29/06; H01L27/112
技術(shù)領(lǐng)域
dielectric,fin,drains,uppermost,vertical,may,fins,be,e.g,in
地域： ID ID Boise

摘要

An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the semiconductor fin and having upper surfaces below an uppermost surface of the semiconductor fin. Another embodiment of a transistor has first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

說(shuō)明書(shū)

FIELD

The present disclosure relates generally to field effect transistors, and, in particular, the present disclosure relates to field effect transistors having a fin.

BACKGROUND

Transistors, such as field effect transistors (FETs), may be used on the periphery of a memory device. These transistors can be located between charge pumps and the string drivers of a memory device that provide voltages to access lines (e.g., word lines) coupled to memory cells and can be used in charge pump circuitry and for the string drivers. Such transistors may be referred to as pass transistors, for example.

Some memory devices may include stacked memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, a stacked memory array may include a plurality of vertical strings (e.g., NAND strings) of memory cells, e.g., coupled in series, between a source and a data line, such as a bit line. For example, the memory cells at a common location (e.g., at a common vertical level) might be commonly coupled to an access line, such as a local access line (e.g., a local word line), that may in turn be selectively coupled to a driver by a pass transistor. For example, pass transistors might couple local access lines to voltage supply circuitry, such as global access lines (e.g., global word lines).

The term vertical may be defined, for example, as a direction that is perpendicular to a base structure, such as a surface of an integrated circuit die. It should be recognized the term vertical takes into account variations from “exactly” vertical due to routine manufacturing and/or assembly variations and that one of ordinary skill in the art would know what is meant by the term vertical.

權(quán)利要求

1
What is claimed is:1. A transistor, comprising:a semiconductor fin;a first dielectric over first and second portions of the semiconductor fin having an uppermost surface below an uppermost surface of the semiconductor fin, wherein the uppermost surface of the semiconductor fin is in a third portion of the semiconductor fin between the first portion of the semiconductor fin and the second portion of the semiconductor fin;a second dielectric over the uppermost surface of the semiconductor fin;a control gate over the second dielectric;a first source/drain in the first portion of the semiconductor fin and having an uppermost surface below a bottommost surface of the control gate and below the uppermost surface of the semiconductor fin; anda second source/drains in the second portion of the semiconductor fin and having an uppermost surfaces below the bottommost surface of the control gate and below the uppermost surface of the semiconductor fin.2. The transistor of claim 1, wherein the control gate extends downward on either side of the third portion of the semiconductor fin to have its bottommost surface at a vertical level above the uppermost surfaces of the source/drains.3. The transistor of claim 2, wherein the second dielectric extends downward on either side of the third portion of the semiconductor fin to have a bottommost surface at the vertical level to which the control gate extends.4. The transistor of claim 1, wherein a portion of the first dielectric extends to a vertical level below a vertical level of the uppermost surfaces of the source/drains.5. The transistor of claim 4, further comprising an isolation region under the portion of the first dielectric that extends to the vertical level below the vertical level of the uppermost surfaces of the source/drains.6. The transistor of claim 1, wherein the transistor is coupled to an access line that is coupled to a memory cell in a vertical string of memory cells.7. The transistor of claim 1, wherein the transistor is a finFET.8. The transistor of claim 1, further comprising a channel in the semiconductor fin.9. The transistor of claim 8, wherein the channel is a convex channel.10. The transistor of claim 1, further comprising an other dielectric over the control gate.11. The transistor of claim 1, further comprising a contact in contact with the control gate.12. The transistor of claim 1, further comprising contacts in contact with the first and second source/drains.13. A transistor, comprising:a semiconductor comprising a first surface at a first vertical level, a second surface at a second vertical level that is above the first vertical level, and sidewalls that extend from the first surface to the second surface;first and second source/drains in the semiconductor that extend below the first surface of the semiconductor without extending above the first surface of the semiconductor;a first dielectric over the first surface of the semiconductor and extending adjacent to the sidewalls of the semiconductor to have an uppermost surface at a third vertical level between the first and second surfaces of the semiconductor;a gate dielectric over the second surface of the semiconductor and extending adjacent to the sidewalls of the semiconductor to have a bottommost surface at the third vertical level; anda control gate over the gate dielectric and extending on either side of the sidewalls of the semiconductor to the third vertical level;wherein uppermost surfaces of the first and second source/drains are at the first vertical level and are below a bottommost surface of the control gate at the third vertical level.14. The transistor of claim 13, wherein the uppermost surfaces of the first and second source/drains are coincident with the first surface of the semiconductor.15. The transistor of claim 14, further comprising a channel in the semiconductor that extends above the uppermost surfaces of the first and second source/drains.16. The transistor of claim 13, wherein the semiconductor further comprises a third surface at a fourth vertical level below the first vertical level, and further comprising isolation regions extending downward from the third surface.17. The transistor of claim 13, further comprising a third dielectric over the control gate and the first dielectric.
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