FIG. 6 is a top view (e.g., in an x-y plane) of a portion of an array of transistors, such as pass transistors, according to an embodiment. For example, the transistors may be field effect transistors (FETs), such as finFETs 600. For example, a plurality of finFETs 600 may be commonly coupled to a control line 6101, and a plurality of finFETs 600 may be commonly coupled to a control line 6102. Each finFET 600 may include a source/drain 615 and a source/drain 617. Note that the finFETs 600 may have a relatively high breakdown voltage (e.g., above about 15 volts to about 80 volts or greater).
FIG. 7 is a cross-sectional view in a y-z plane taken along line 7-7 in FIG. 6, where cross-hatching is omitted for clarity. Note that the cross-section in FIG. 7 corresponds to the cross-section in FIG. 2. Note that the vertical direction (e.g., the z direction) may be perpendicular to the x-y plane in FIG. 6.
A dielectric 710 may be over a surface in semiconductor 212 that is at a vertical level Z1 in semiconductor 212 and that is below the uppermost surface (e.g., at the vertical level Z0) of semiconductor 212. An uppermost surface of dielectric 710 may be below the uppermost surface of semiconductor 212 for some embodiments.
