In FIG. 11E, a control gate 820 is formed over dielectric 810 from a conductor 1150. For example, 1150 may be formed over the exposed upper surface of dielectric 710 and the exposed surfaces of dielectric 810. Conductor 1150 may then be subsequently removed so that control gate 820 is over a portion of the upper surface of dielectric 710, over dielectric 810, and thus over the uppermost (e.g., the top) surface of semiconductor fin 720 at vertical level Z₀, as shown in FIG. 11E. In an alternative example, the portions of dielectric 810 and the portions of dielectric 710 uncovered by control gate 820 in FIG. 11E may be covered, e.g., by a mask, while conductor 1150 is deposited to form control gate 820.

Subsequently, for some embodiments, source/drain 615 and source/drain 617 may be formed in semiconductor fin 720 so that the upper (e.g., the uppermost) surfaces of source/drain 615 and source/drain 617 are at the vertical level Z₁ below the uppermost surface of semiconductor fin 720 at the vertical level Z₀. For example, the upper surfaces of source/drain 615 and source/drain 617 may be coincident with surfaces of semiconductor fin 720 that are at the vertical level Z₁ such that source/drain 615 and source/drain 617 do not extend above those surfaces of semiconductor fin 720.