The control gate 820 of the finFET 600 may be over dielectric 810. For example, control gate 820 might be confined to vertical levels above the vertical level of the upper surfaces of the source/drains 615 and 617. That is, control gate 820 may extend downward on either side of semiconductor fin 720 and may terminate at a vertical level above the vertical level Z₁, for example. Control gate 820 may terminate at an upper surface of dielectric 710 so that a portion of dielectric 710 is between the upper surfaces of source/drains 615 and 617 and the (e.g., lowermost) ends of control gate 820, for example.

A channel 975 may be in the upper portion 1110 of semiconductor fin 720. For example, channel 975 may extend above the upper surfaces of source/drains 615 and 617.

A dielectric 1160, e.g., a bulk dielectric, may then be formed over dielectric 710 and control gate 820, as shown in FIG. 11F. One example for dielectric 1160 would be a doped silicate glass. Examples of doped silicate glasses include BSG (borosilicate glass), PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass). Another example for dielectric 1160 would be TEOS (tetraethylorthosilicate), silicon dioxide, etc.