FIGS. 12A-12D are cross-sectional views, e.g., in the x-z plane, of a transistor 1200 (FIG. 12C), such as a field effect transistor, during various stages of fabrication. Note that the transistor 1200 may have a relatively high breakdown voltage (e.g., above about 15 volts to about 80 volts or greater). For example, transistor 1200 may be a pass transistor, e.g., coupled between an access-line driver and an access line commonly coupled to a plurality of memory cells in a memory array, such as a stacked memory array.

In FIG. 12A, a plurality of semiconductor fins (e.g., pillars) 1210, such as semiconductor fins 1210₁ to 1210₄, may be formed by patterning the uppermost surface (e.g., at vertical level z=Z₀′) of a semiconductor 1212 and removing portions of semiconductor 1212 exposed by the pattern. For example, a mask (not shown), e.g., imaging resist, such as photo-resist, may be formed over the uppermost surface of semiconductor 1212 and patterned to define regions of semiconductor 1212 for removal. The regions defined for removal may be subsequently removed, e.g., by etching, stopping at a vertical level z=Z₁′ and leaving semiconductor fins 1210 under the mask and forming openings 1215, where semiconductor 1212 was removed, between the semiconductor fins 1210. Uppermost surfaces of semiconductor fins 1210 may be at vertical level Z₀′, e.g., coincident with the uppermost surface of semiconductor 1212, for example. Note that semiconductor 1212 might be conductively doped, e.g., to have a p-type conductivity.