A P well 5 is disposed in the active region 100 at the front side of the substrate; an N-type emitter 6 is disposed in the P well 5. A gate oxide layer 3 is disposed at the front side of the substrate, a polysilicon gate 4 is disposed at a surface of the gate oxide layer 3, and the polysilicon gate 4 is also covered by the silicon oxide layer (the oxide dielectric layer 7). The polysilicon gate 4 is disposed between two adjacent P wells 5, and between a P well 5 at boundary of the active region 100 and the terminal structure 200 and a field limiting ring 2. An emitter metal structure 8 is disposed on the P well 5, the silicon oxide layer and the emitter metal structure 8 is covered by a passivation layer 9. The function of the passivation layer 9 is used for preventing the surface of the chip from contaminating of the external ions. In the embodiment, the material of the passivation layer 9 is SiN.

In the embodiment as shown in FIG. 2, both the field stop layer 1 and the emitter 6 are the N+ type, the back side P-type structure 10 is the P+ type.

As shown in FIG. 3, a manufacturing method of a field stop reverse conducting insulated gate bipolar transistor comprises the following steps:

S310, providing an N-type substrate, forming an N-type field stop layer at the back side of the N-type substrate.

Referring to FIG. 4A, in the embodiment, a dopant concentration of the N+ field stop layer 1 is higher than that of the substrate.

S320, performing a first phrase front side process.