S321, implanting P-type dopant at the front side of the substrate by photoetching, after thermal diffusion forming a field limiting ring 2 as the high voltage-resisting structure.

In the embodiment the field limiting ring is used as the high voltage-resisting structure. In other embodiments the field plate can be also used as the high voltage-resisting structure. Or it can be the high voltage-resisting structure of the field limiting ring plus the field plate, or the high voltage-resisting structure for other terminals.

S322, growing a field oxide layer 14 at the front side of the substrate, and photoetching and etching the field oxide layer 14 on the active region area.

FIG. 4B shows a cross-section view of the field stop reverse conducting insulated gate bipolar transistor after the step S322 is performed.

S323, growing a gate oxide layer at the front side of the substrate, and forming a polysilicon layer at a surface of the gate oxide layer.

FIG. 4C shows a cross-section view of the field stop reverse conducting insulated gate bipolar transistor after the step S323 is performed. In the embodiment, growing the gate oxide layer 3 with a thickness of 600 angstrom to 1500 angstrom by the thermal oxidation, then depositing and forming the polysilicon layer 4 at the surface of the gate oxide layer 3.

S324, removing a surplus part of the polysilicon layer and the gate oxide layer by photoetching and etching, for forming a polysilicon gate, and ion-implanting P-type dopant to the substrate, forming the P well after driving-in.