The novel well structure 424 which encloses or houses the gate driver 411 is of similar construction as the previously discussed well-structure 324 and corresponding features have been provided with corresponding reference numerals to ease comparison. The gate driver 411 comprises an inverter comprising cascaded PMOS-NMOS transistor pair 401, 403 with a driver output 404 electrically coupled or connected to a gate terminal of the LDNMOS power transistor 407 on a high side of the class D output stage. Drain, gate and source diffusions or terminals of the NMOS transistor 403 of the gate driver 411 are arranged in a vertical wall section 429 of P+ polarity semiconductor material as illustrated on FIG. 4B. This vertical wall section 429 is a part of an inner P-well diffusion of the novel well structure 424. The novel well structure 424 additionally comprises an N+ polarity transistor body diffusion 435 arranged in abutment to the opposing wall segments of the vertical wall section 429 and above the horizontal P+ buried layer 427. Drain, gate and source diffusions or terminals of the PMOS transistor 401 of the gate driver 411 are arranged in the N+ polarity transistor body diffusion 435 as illustrated on FIG. 4B). The gate terminals of the PMOS-NMOS transistor pair 401, 403 are electrically connected via a wire or trace 404 to form an input 414 of the gate driver. The PMOS source terminal and the NMOS drain terminal of invertor or transistor pair 401, 403 are electrically connected via a wire or trace 415 to form the output node or terminal 425 of the gate driver 411. The latter output node 425 is connected to the gate of the high side power LDNMOS transistor 407 of the class D output stage. The electrical wire or trace pattern 412a establishes electrical connection between the source of the NMOS driver transistor 403 and the inner P-well diffusion via the indicated black rectangular well contact. The electrical wire or trace pattern 412a likewise establishes electrical connection between the source of the NMOS driver transistor 403 and the outer N-well diffusion 430 via the well contact (illustrated by white rectangle symbol) embedded in the diffusion 430. The electrical wire or trace pattern 412a accordingly connects the high side negative supply voltage port of the gate driver 411 to the inner P-well diffusion, the outer N-well diffusion and to the output terminal OUT 412 of the class D output stage. The other electrical connection, wire or trace 412b establishes a further electrical connection between the inner P-well diffusion and the outer N-well diffusion via respective well contacts. The coupling of the parasitic well capacitance 413 (NBL-epi Cap) to the P type epitaxial semiconductor substrate 422 is schematically illustrated by the capacitor symbol 413 on FIG. 4A) and FIG. 4B) which illustrate how the parasitic well capacitance 413 has been eliminated from the regulated DC voltage node 406, GVDD_FLOAT. The parasitic well capacitance 413 has been moved and connected to the low impedance output terminal OUT 412 of the class D output stage leading to the previously discussed benefits.