Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate
地域：
Montrouge
摘要
An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.
說明書
This application claims priority from French Application for Patent No. 1652717 filed Mar. 30, 2016, the disclosure of which is incorporated by reference.
Embodiments relate to integrated circuits and more particularly MOS transistors with hybrid operation produced on substrates of silicon on insulator type, commonly referred to by those skilled in the art by the acronym “SOI”, in particular a substrate of the fully depleted silicon on insulator type, known to those skilled in the art by the acronym “FDSOI”.
MOS transistors with hybrid operation are known, which are of interest notably for electrostatic discharge (ESD) protection applications. A person skilled in the art will for example be able to refer to U.S. Pat. No. 9,019,666 (incorporated by reference) which describes this type of transistor.
These transistors are produced on bulk substrates. Now, electrical simulations have shown (see, for example, Galy, et al., “BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology”, EUROSOI-ULIS 2015, 26-28 Jan. 2015, Bologna, Italy (incorporated by reference)), that there would be advantages from an electrical point of view in producing these transistors with hybrid operation on a substrate of FDSOI type for an ESD protection application.
However, the very small thickness of the semiconductive film (typically of the order of 7 nm) does not make it possible to directly produce a contact on an FDSOI substrate for this type of transistor.
權(quán)利要求
The invention claimed is:1. A method for producing at least one substrate contact for an MOS transistor produced in and on an active zone of a substrate of silicon on insulator type, comprising:forming on top of the active zone a gate region of the transistor having a rectilinear part situated between source and drain regions of the transistor and extended by a first forked part which includes a first part extending perpendicular to the rectilinear part over a portion of the semiconductor film where the source and drain regions are not present, a second part extending perpendicular to the first part, and a third part extending perpendicular to the first part and spaced apart from said second part; forming at least one first raised semiconductive region above the active zone and at least partly positioned between the second and third parts of said first forked part; and forming said at least one substrate contact electrically coupled to said at least one first raised semiconductive region. 2. The method according to claim 1 , wherein forming the gate region further comprises forming a second forked part extending said rectilinear part opposite the first forked part, the second forked part including a fourth part extending perpendicular to the rectilinear part over a further portion of the semiconductor film where the source and drain regions are not present, a fifth part extending perpendicular to the fourth part, and a sixth part extending perpendicular to the fourth part and spaced apart from said fifth part, the method further comprising:forming a second raised semiconductive region above the active zone and at least partly positioned between the fifth and sixth parts of said second forked part; and forming a second substrate contact for the first transistor electrically coupled to said second raised semiconductive region. 3. The method according to claim 1 , wherein forming the at least one first raised semiconductive region comprises epitaxially growing a semiconductive material. 4. The method according to claim 1 , wherein forming said at least one substrate contact is performed on the at least one first raised semiconductive region. 5. An integrated electronic device, comprising:a semiconductive film above a buried insulating layer which is situated above a supporting substrate, an active zone within the semiconductive film, at least one first MOS transistor produced in and on the active zone and comprising a gate region situated above the active zone, the gate region having a rectilinear part situated between source and drain regions, and at least one first forked part which extends the rectilinear part and includes a first part extending perpendicular to the rectilinear part over a portion of the semiconductor film where the source and drain regions are not present, a second part extending perpendicular to the first part, and a third part extending perpendicular to the first part and spaced apart from said second part, at least one first raised semiconductive region situated above the active zone and at least partly positioned between the second and third parts of said first forked part, and at least one first substrate contact for the first transistor electrically coupled to said first raised semiconductive region. 6. The device according to claim 5 , wherein the gate region comprises a second forked part extending said rectilinear part opposite the first forked part and including a fourth part extending perpendicular to the rectilinear part over a further portion of the semiconductor film where the source and drain regions are not present, a fifth part extending perpendicular to the fourth part, and a sixth part extending perpendicular to the fourth part and spaced apart from said fifth part, further comprising:a second raised semiconductive region situated above the active zone and at least partly positioned between the fifth and sixth parts of said second forked part, and a second substrate contact for the first transistor electrically coupled to said second raised region. 7. The device according to claim 5 , further comprising, within the supporting substrate, a semiconductive well situated under said active part and a well contact for biasing of said well. 8. The device according to claim 5 , wherein the at least one substrate contact is situated on the first raised semiconductive region. 9. The device according to claim 5 , wherein the semiconductive film is fully depleted. 10. An integrated electronic device, comprising:a semiconductive film above a buried insulating layer which is situated above a supporting substrate, an active zone within the semiconductive film, at least one first MOS transistor produced in and on the active zone and comprising a gate region situated above the active zone, the gate region having a rectilinear part situated between source and drain regions, and at least one first forked part which extends the rectilinear part, wherein the forked part comprises:an extension extending at right angles on either side of the rectilinear part out of the source and drain regions, a first branch connected to said extension and extending in the extension of the source region, and a second branch connected to said extension and extending in the extension of the drain region, at least one first raised semiconductive region situated above the active zone, wherein the at least one first raised semiconductive region extends at least partly between the first branch and second branch, and at least one first substrate contact for the first transistor electrically coupled to said first raised semiconductive region. 11. The device according to claim 10 , further comprising a number of MOS transistors having rectilinear parts extending in parallel and being mutually electrically connected via the at least one forked part. 12. The device according to claim 11 , wherein said extension forms a single line of gate material at a right angle to each rectilinear part. 13. The device according to claim 11 , wherein neighboring transistors have one of a source region or a drain region in common. 14. A device, comprising:a semiconductive film above a buried insulating layer which is situated above a supporting substrate, an active zone within the semiconductive film including an elongated source region, an elongated drain region extending in parallel with the elongate source region and a channel region between the elongated source and drain regions, a gate region comprising:a first rectilinear part extending over the channel region parallel to the elongated source and drain regions, a second rectilinear part extending perpendicular to the first rectilinear part over a portion of the semiconductor film where the elongated source and drain regions are not present, a third rectilinear part extending perpendicular to the second rectilinear part over said portion of the semiconductor film, and a fourth rectilinear part extending perpendicular to the second rectilinear part over said portion of the semiconductor film and spaced apart from said third rectilinear part, an epitaxial region on said portion of the semiconductor film and located between the third and fourth rectilinear parts, and a substrate contact for the transistor electrically coupled to said epitaxial region. 15. The device of claim 14 , further comprising:a doped well in the supporting substrate underneath the active zone; and means for biasing said doped well. 16. The device of claim 14 , wherein said gate region further comprises:a fifth rectilinear part extending perpendicular to the first rectilinear part over a further portion of the semiconductor film where the elongated source and drain regions are not present, wherein said portion of the semiconductor film and said further portion of the semiconductor film are at opposite ends of the elongated source and drain regions, a sixth rectilinear part extending perpendicular to the fifth rectilinear part over said further portion of the semiconductor film, and a seventh rectilinear part extending perpendicular to the fifth rectilinear part over said further portion of the semiconductor film and spaced apart from said sixth rectilinear part, and further comprising:a further epitaxial region on said further portion of the semiconductor film and located between the sixth and seventh rectilinear parts, and a further substrate contact for the transistor electrically coupled to said further epitaxial region. 17. The device of claim 14 , wherein said gate region further comprises:a fifth rectilinear part extending perpendicular to the second rectilinear part over said portion of the semiconductor film and spaced apart from said fourth rectilinear part, further comprising:a further epitaxial region on said portion of the semiconductor film and located between the fourth and fifth rectilinear parts, and a further substrate contact for the transistor electrically coupled to said further epitaxial region.
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