The inventors have notably observed that, by comparison to a structure that is functionally equivalent but whose substrate contacts are produced by additional transistors such as those described in the U.S. application Ser. No. 15/041,593 (French Appl. No. 1556515), a reduction of the surface area of the imprint of the circuit is obtained that is of the order of 30%.

That is notably due, in the case where the contacts are made by additional transistors to the need to produce isolation trenches between each transistor used to take the substrate contact in order to reduce the spurious effects.

FIG. 6 illustrates an embodiment in which the MOS transistor TR comprises a second forked part G4, opposite the first forked part G2, comprising a second extension G40 which extends at right angles on either side of the rectilinear gate part G1.

The second forked part G4 further comprises a third branch G41 and a fourth branch G42 extending from the second extension G40 in the extension of the source and drain regions S and D.

A second additional raised silicon region 6 has also been produced above the silicon film 1, between the third branch G41 and the fourth branch G42, by epitaxial rework. The biasing of this region allows for a second substrate contact PCB2 and therefore makes it possible to bias the substrate B of the transistor TR.

Thus, the device comprises two forked parts G2 and G4 and two substrate contacts PCB and PCB2 produced symmetrically on either side of the transistor TR.

The addition of this second substrate contact PCB2 makes it possible to more effectively bias the substrate B of the transistor TR.