Furthermore, as illustrated in FIG. 7, the device can be considered functionally as an MOS transistor T with four gates, also known to those skilled in the art by the designation “G⁴-FET”, and comprising 6 contacts.

In this mode of operation, the two contacts PCB and PCB2 are used as the electrodes of the transistor T. For example, the first contact PCB corresponds to the source and the second contact PCB2 corresponds to the drain.

The source S and the drain D of the transistor TR are used as two gates of a P-channel JFET transistor. They can therefore here be biased in order to modulate the current flowing between the source PCB and the drain PCB2 of the transistor T.

The gate G and the rear gate of the transistor TR, linked respectively to the contacts PCG and BG, can also be biased in order to modulate the current, and also the resistance value R of the substrate B. These two gates form the other two gates of the four-gate transistor T.

It should be noted that the embodiments presented here are in no way limiting.

More specifically in the devices described previously, the forked parts and the raised regions 5, 51, 52, 53, 6 are separated by a thin space and mutually electrically insulated for example by insulating spacers (not represented in the interests of clarity of the figures) situated on the flanks of the forked parts.

This makes it possible to have different contacts for the gate and the substrate. It then becomes possible to have particular embodiments as described in U.S. Pat. No. 9,019,666.