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Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate

專利號(hào)
US10096708B2
公開日期
2018-10-09
申請(qǐng)人
STMicroelectronics SA(FR Montrouge)
發(fā)明人
Sotirios Athanasiou; Philippe Galy
IPC分類
H01L29/78; H01L27/12; H01L23/528; H01L21/84; H01L29/66; H01L21/74; H01L29/786
技術(shù)領(lǐng)域
forked,transistor,substrate,gate,region,raised,drain,tr,contact,mos
地域: Montrouge

摘要

An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.

說明書

1 2 3 4 5 6 7 8 9 10 11 12

More specifically, it is possible to connect a first resistive element between the source and the substrate of the MOS transistor and a second resistive element between the gate and the source of the MOS transistor, the gate and the substrate of the transistor not being connected together.

A combined bipolar and MOS effect is then obtained through the drain-substrate capacitances and through the drain-gate capacitances. That said, this combined effect is not amplified because of the absence of connection between the substrate and the gate of the transistor.

It would also be possible, in the context of a reversible operation, to leave the substrate and the gate of the MOS transistor floating. The bipolar and MOS effect is then obtained by the capacitive gate-substrate coupling.

So as to have an amplified effect, it is possible to electrically link the gate and the substrate of the transistor, and also advantageously provide for a resistor to be connected between the gate and the ground, the value of which can be adjusted to raise the value of the trigger threshold of the device, as explained in U.S. Pat. No. 9,019,666.

In this respect, it would be perfectly possible to envisage having the forked parts and said raised regions in contact, which amounts to electrically connecting the substrate B and the gate G of the transistor TR by having only a single contact situated for example on the gate region.

Furthermore, in the embodiment illustrated in FIG. 5, it would be possible to equip each transistor with a second forked part and a second substrate contact, as illustrated in FIG. 6.

權(quán)利要求

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