U.S. application patent Ser. No. 15/041,593 filed Feb. 11, 2016 (corresponding to French Application for Patent No. 1556515), incorporated by reference, describes means that make it possible to produce a substrate contact by the use of additional junction-free transistor(s) as connection element(s). Although satisfactory, this solution can however, in some cases, generate spurious effects and offers an integration density which can prove limited in certain applications.

Thus, according to one implementation and embodiment, it is proposed to provide a substrate contact for a transistor produced in a substrate of SOI type, in particular of FDSOI type, resulting in reduced spurious effects, notably because of a more compact geometry.

According to one aspect, there is proposed a method for producing at least one substrate contact for an MOS transistor produced in and on an active zone of a substrate of silicon on insulator type, comprising:

• • formation on top of the active zone of a gate region of the transistor having a rectilinear part situated between the source and drain regions of the transistor and extended by at least one first forked part,
  • formation of at least one first raised semiconductive region above the active zone and at least partly within said first forked part, and
  • formation of said at least one substrate contact electrically coupled to, for example on, said at least one first raised semiconductive region.