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Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate

專利號
US10096708B2
公開日期
2018-10-09
申請人
STMicroelectronics SA（FR Montrouge）
發(fā)明人
Sotirios Athanasiou; Philippe Galy
IPC分類
H01L29/78; H01L27/12; H01L23/528; H01L21/84; H01L29/66; H01L21/74; H01L29/786
技術(shù)領(lǐng)域
forked,transistor,substrate,gate,region,raised,drain,tr,contact,mos
地域： Montrouge

摘要

An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.

說明書

1 2 3 4 5 6 7 8 9 10 11 12

According to one embodiment, the device can comprise, within the supporting substrate, a semiconductive well situated under said active zone, and a well contact intended to bias said well.

According to one embodiment, the device can comprise a number of MOS transistors of which the rectilinear gate parts are parallel and mutually electrically connected via their forked part, so that all of the extensions of the transistors form a single line of gate material at right angles to each rectilinear gate part and from which extend said corresponding branches.

Two neighboring transistors can have their source regions or their drain regions in common.

According to one embodiment, at least one substrate contact is situated on the corresponding raised semiconductive region.

As a variant, at least one raised semiconductive region is in contact with at least one forked part of the gate region and at least one substrate contact is situated on said gate region.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features of the invention will become apparent on studying the detailed description of non-limiting embodiments, and the attached drawings in which:

FIGS. 1 to 7 illustrate embodiments of a substrate contact for a transistor.

 DETAILED DESCRIPTION

FIG. 1 illustrates a plan view of an integrated device DIS according to one embodiment, for which FIGS. 2 and 3 are cross-sectional views along the lines II-II and III-III of FIG. 1.

權(quán)利要求

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