The device DIS therefore comprises the transistor TR situated in and on a substrate of FDSOI type comprising a substrate contact produced simply and accurately by epitaxial rework and siliciding. Thus, the contact is close to the substrate of the transistor which makes it possible to reduce the spurious capacitive effects and the substrate access resistance.

FIG. 4 illustrates a schematic representation of the device from an electrical point of view.

Represented therein are the transistor TR, comprising its drain D, source S and gate G regions, the contacts PCS, PCD, PCG and PCB, and the contact of the well BG.

A capacitor C schematically represents the capacitor formed under the transistor TR by the semiconductive film 1, the insulating layer 2 and the well 3.

The gate contacts situated on each of the branches G21 and G22 are represented by one and the same contact PCG.

Such a device notably makes it possible to obtain a very significant current gain, of the order of 10⁵.

FIG. 5 illustrates an embodiment in which the device DIS comprises a number of analog MOS transistors TR1, TR2 and TR3 similar to that described previously and illustrated in FIGS. 1 to 4.

The three transistors (the number three not being limiting) are produced in and on the same silicon film 1, and their gates are mutually electrically connected via the extension of their respective forked part.