The device can therefore be considered as having a common gate G, comprising 3 rectilinear gate parts G10, G11 and G12, and an extension G3 at right angles to the three gate lines from which extend a number of branches G30, G31, G32 and G33 in the extension of the source and drain regions of each transistor.

Here, each transistor is produced in such a way as to have its source region and/or its drain region in common with the neighboring transistor.

Thus, the transistor TR1 comprises the first rectilinear part G10 and the source and drain regions D1 and S1, the transistor TR2 comprises the second rectilinear part G11 and the source and drain regions S1 and D2, and the third transistor TR3 comprises the third rectilinear part G12 and the source and drain regions D2 and S2.

Each transistor TR1, TR2 or TR3 also comprises a raised region 51, 52 or 53 in the extension of its gate, between the branches of its forked part, and on which is produced a zone of metal silicide (not represented) allowing for a substrate contact.

The device also comprises a well contact BG making it possible to bias the well common to each transistor via the rear face. Given that the wells of the transistors TR1, TR2 and TR3 are common, the contact BG makes it possible to bias each of the transistors via its rear face.

The production of the substrate contacts on the raised silicon regions makes it possible to obtain a more compact structure.