Aspect ratio trapping (ART) for fabricating vertical semiconductor devices
地域：
CA
CA Santa Clara
摘要
Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
說明書
This application is a U.S. National Phase application under 35 U.S.C. § 371 of International Application No. PCT/US2014/032203, filed Mar. 28, 2014, entitled “ASPECT RATIO TRAPPING (ART) FOR FABRICATING VERTICAL SEMICONDUCTOR DEVICES,” the entire contents of which are incorporated herein by reference.
Embodiments of the invention are in the field of semiconductor devices and, in particular, aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from.
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, or gate-all-around devices, such as nanowires, have become more prevalent as device dimensions continue to scale down. Many different techniques have been attempted to reduce channel or external resistance of such transistors. However, significant improvements are still needed in the area of channel or external resistance suppression.
權(quán)利要求
What is claimed is:1. A semiconductor device, comprising:a substrate with an uppermost surface having a first lattice constant; a first source/drain region disposed on the uppermost surface of the substrate and having a second, different, lattice constant; a vertical channel region disposed on the first source/drain region; a second source/drain region disposed on the vertical channel region, wherein the second source/drain region has an upper lateral portion and a lower vertical portion, the lower vertical portion on the vertical channel region, and the lower vertical portion having first and second sides, wherein the upper lateral portion extends beyond both the first and second sides of the lower vertical portion, and wherein the upper lateral portion has a lateral width greater than a lateral width of the vertical channel region; and a gate stack disposed on and completely surrounding a portion of the vertical channel region, wherein the gate stack is not in physical contact with the upper lateral portion of the second source/drain region. 2. The semiconductor device of claim 1 , further comprising:a plurality of lattice defects confined to the first source/drain region, wherein the vertical channel region is essentially defect-free. 3. The semiconductor device of claim 1 , wherein the first and second source/drain regions comprise a semiconductor material different from a semiconductor material of the vertical channel region. 4. The semiconductor device of claim 3 , wherein the semiconductor material of the first and second source/drain regions is lattice mismatched from the semiconductor material of the vertical channel region, and wherein the first and second source/drain regions impart a strain to the vertical channel region. 5. The semiconductor device of claim 1 , further comprising:a first contact disposed on the uppermost surface of the substrate and electrically coupled to the first source/drain region through the substrate; a second contact disposed on the second source/drain region; and a gate contact disposed on a horizontal extension of the gate stack. 6. The semiconductor device of claim 1 , wherein the first source/drain region is a drain region, and wherein the second source/drain region is a source region. 7. The semiconductor device of claim 1 , wherein the first source/drain region is a source region, and wherein the second source/drain region is a drain region. 8. The semiconductor device of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode. 9. The semiconductor device of claim 1 , wherein a conductivity type of the first source/drain region is the same as a conductivity type of the second source/drain region, and wherein the semiconductor device is a MOS-FET device. 10. The semiconductor device of claim 1 , wherein a conductivity type of the first source/drain region is opposite to a conductivity type of the second source/drain region, and wherein the semiconductor device is a tunnel FET device. 11. A semiconductor device, comprising:a substrate having a surface; a first source/drain region disposed on the surface of the substrate; a vertical channel region disposed on the first source/drain region; a plurality of lattice defects confined to the first source/drain region, wherein the vertical channel region is essentially defect-free; a second source/drain region disposed on the vertical channel region, wherein the second source/drain region has an upper lateral portion and a lower vertical portion, the lower vertical portion on the vertical channel region, and the lower vertical portion having first and second sides, wherein the upper lateral portion extends beyond both the first and second sides of the lower vertical portion, and wherein the upper lateral portion has a lateral width greater than a lateral width of the vertical channel region; and a gate stack disposed on and completely surrounding a portion of the vertical channel region, wherein the gate stack is not in physical contact with the upper lateral portion of the second source/drain region. 12. The semiconductor device of claim 11 , wherein the first and second source/drain regions comprise a semiconductor material different from a semiconductor material of the vertical channel region. 13. The semiconductor device of claim 12 , wherein the semiconductor material of the first and second source/drain regions is lattice mismatched from the semiconductor material of the vertical channel region, and wherein the first and second source/drain regions impart a strain to the vertical channel region. 14. The semiconductor device of claim 11 , further comprising:a first contact disposed on the surface of the substrate and electrically coupled to the first source/drain region through the substrate; a second contact disposed on the second source/drain region; and a gate contact disposed on a horizontal extension of the gate stack. 15. The semiconductor device of claim 11 , wherein the first source/drain region is a drain region, and wherein the second source/drain region is a source region. 16. The semiconductor device of claim 11 , wherein the first source/drain region is a source region, and wherein the second source/drain region is a drain region. 17. The semiconductor device of claim 11 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode. 18. The semiconductor device of claim 11 , wherein a conductivity type of the first source/drain region is the same as a conductivity type of the second source/drain region, and wherein the semiconductor device is a MOS-FET device. 19. The semiconductor device of claim 11 , wherein a conductivity type of the first source/drain region is opposite to a conductivity type of the second source/drain region, and wherein the semiconductor device is a tunnel FET device. 20. A method of fabricating a semiconductor device, the method comprising:forming an insulator layer on a surface of a substrate; patterning the insulator layer to form an opening in the insulator layer, the opening exposing a portion of the surface of the substrate; forming a first source/drain region in the opening, on the surface of the substrate; forming a vertical channel region in the opening, on the first source/drain region; forming a second source/drain region in the opening, on the vertical channel region, wherein the second source/drain region has an upper lateral portion and a lower vertical portion, the lower vertical portion on the vertical channel region, and the lower vertical portion having first and second sides, wherein the upper lateral portion extends beyond both the first and second sides of the lower vertical portion, and wherein the upper lateral portion has a lateral width greater than a lateral width of the vertical channel region; recessing the insulator layer to expose a portion of the vertical channel region; and forming a gate stack on and completely surrounding an exposed portion of the vertical channel region, wherein the gate stack is not in physical contact with the upper lateral portion of the second source/drain region. 21. The method of claim 20 , wherein forming the first source/drain region comprises forming a plurality of lattice defects confined to the first source/drain region, wherein the vertical channel region is formed essentially defect-free. 22. The method of claim 20 , wherein forming the first source/drain region comprises forming the first source/drain region having a lattice constant different than a lattice constant of the surface of the substrate. 23. The method of claim 20 , wherein forming the second source/drain region in the opening comprises forming a first portion of the second source/drain region in the opening, and forming a second portion of the second source/drain region above the opening and on a portion of an uppermost surface of the insulator layer. 24. The method of claim 20 , wherein forming the first source/drain region comprises forming a drain region, and wherein forming the second source/drain region comprises forming a source region. 25. The method of claim 20 , wherein forming the first source/drain region comprises forming a source region, and wherein forming the second source/drain region comprises forming a drain region.
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