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Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

專利號(hào)
US10096709B2
公開日期
2018-10-09
申請人
Intel Corporation(US CA Santa Clara)
發(fā)明人
Van H. Le; Benjamin Chu-Kung; Gilbert Dewey; Jack T. Kavalieros; Ravi Pillarisetty; Willy Rachmady; Marko Radosavljevic; Matthew V. Metz; Niloy Mukherjee; Robert S. Chau
IPC分類
H01L29/78; H01L29/423; H01L29/66; H01L29/786; H01L21/8238; H01L29/267; H01L29/08; H01L29/165; H01L29/739
技術(shù)領(lǐng)域
region,drain,source,vertical,channel,in,gate,stack,layer,embodiment
地域: CA CA Santa Clara

摘要

Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

說明書

In an embodiment, the source region(s) 110 is formed on vertical channel region 106 by a deposition process such as, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). In one embodiment, the source region 110 is in situ doped with impurity atoms. In one embodiment, the source region 110 is doped with impurity atoms subsequent to formation. In one embodiment, the source region 110 is in situ doped with impurity atoms and further doped subsequent to formation. It is to be appreciated that the source region 110 may be composed of a like or different semiconductor material as that of the vertical channel region 110. In one embodiment, the source region 110 is composed of a crystalline silicon, silicon/germanium, germanium, or germanium tin layer, which may be doped with a charge carrier, such as but not limited to, phosphorus, arsenic, boron or a combination thereof. In another embodiment, the source region 110 is composed of a group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof, which may be doped with a charge carrier, such as but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

權(quán)利要求

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