It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present invention. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a gate-all-around device. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) or smaller technology node. Embodiments herein may be applicable for improving transistor layout density and for mitigating trends toward increases in contact resistance.

FIG. 2 illustrates a computing device 200 in accordance with one implementation of the invention. The computing device 200 houses a board 202. The board 202 may include a number of components, including but not limited to a processor 204 and at least one communication chip 206. The processor 204 is physically and electrically coupled to the board 202. In some implementations the at least one communication chip 206 is also physically and electrically coupled to the board 202. In further implementations, the communication chip 206 is part of the processor 204.