In an embodiment, a semiconductor device, includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region. A plurality of lattice defects is confined to the first source/drain region. The vertical channel region is essentially defect-free. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

In one embodiment, the first and second source/drain regions are composed of a semiconductor material different from a semiconductor material of the vertical channel region.

In one embodiment, the semiconductor material of the first and second source/drain regions is lattice mismatched from the semiconductor material of the vertical channel region, and the first and second source/drain regions impart a strain to the vertical channel region.

In one embodiment, the semiconductor device further includes a first contact disposed on the surface of the substrate and electrically coupled to the first source/drain region through the substrate. A second contact is disposed on the second source/drain region. A gate contact is disposed on a horizontal extension of the gate stack.

In one embodiment, the first source/drain region is a drain region, and the second source/drain region is a source region.

In one embodiment, the first source/drain region is a source region, and the second source/drain region is a drain region.

In one embodiment, the gate stack includes a high-k gate dielectric layer and a metal gate electrode.