More generally, embodiments described herein involve implementation of aspect ratio trapping (ART) by forming openings or trenches in an insulating layer formed on a silicon substrate (or other) surface. Non-latticed matched materials for vertical transistors are then grown directly on portions of the substrate exposed by the openings. Aspect ratio trapping may be implemented for a variety of purposes such as, but not limited to, (1) defect reduction in mismatched materials for successful integration onto Si, and (2) enabling vertical device architectures that allows for gate length (Lg) scaling and leakage reduction. The unifying combination of these two advantages is a new outcome achievable by ART approaches described herein. Thus, embodiments may be used to achieve one or more of, (a) using ART openings or trenches to grow films while trapping defects, (b) growing doped source/drain (S/D) materials at opening or trench bottoms to trap defects in the S/D materials, (c) upon such defect confinement or capture, an intrinsic channel material may be grown, and (d) a top layer may then be grown to form another contact which may be grown to the top of the opening and then laterally expanded.