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Transistor, semiconductor device, and electronic device

專利號
US10096720B2
公開日期
2018-10-09
申請人
Semiconductor Energy Laboratory Co., Ltd.(JP Atsugi-shi, Kanagawa-ken)
發(fā)明人
Yoshinori Ando
IPC分類
H01L27/12; H01L29/786; H01L29/66
技術(shù)領(lǐng)域
layer,transistor,insulating,electrode,in,109_1b,oxide,be,or,wiring
地域: Atsugi-shi, Kanagawa-ken

摘要

To provide a semiconductor device with high design flexibility. A first transistor and a second transistor having different electrical characteristics from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. A semiconductor layer where a channel of the first transistor is formed and a semiconductor layer where a channel of the second transistor is formed are formed using semiconductor materials having different electron affinities. When an oxide semiconductor is used for the semiconductor layer, an insulating layer containing excess oxygen is used as an insulating layer below the semiconductor layer. By increasing the thickness of the insulating layer, a large amount of oxygen can be supplied to the semiconductor layer.

說明書

The low-concentration p-type impurity regions 284 can be formed in such a manner that an impurity element is added with the use of the electrode 287 as a mask after the formation of the electrode 287 and before the formation of the sidewall 288. In other words, the low-concentration p-type impurity regions 284 can be formed in a self-aligned manner. After the sidewall 288 is formed, the high-concentration p-type impurity regions 285 are formed. Note that the low-concentration p-type impurity regions 284 have the same conductivity type as the high-concentration p-type impurity regions 285, and have a lower concentration of the impurity imparting the conductivity type than the high-concentration p-type impurity regions 285. The low-concentration p-type impurity regions 284 are not necessarily provided depending on circumstances.

The transistor 281 is electrically isolated from other transistors by an element isolation layer 414. The element isolation layer can be formed by a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like.

權(quán)利要求

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