The hard mask layer 200 may be disposed on top of the semiconductor structure 301 as an etching mask for an etching process in forming the edge emitting laser, and to cover the top surface of the semiconductor structure to prevent any top growth of III-V semiconductors on top of the semiconductor structure 301. The hard mask layer 200 may include silicon oxide (SiO2), silicon nitride (Si3N4), boron nitride (BN), metal, metal nitride, and/or metal oxide and may have a thickness in a range from about 10 nm to about 100 nm. The hard mask layer 200 may have its shape and size the same as those of the semiconductor structure 301 in the X-Y plan, and may have a width in the first direction, X direction, from about 0.5 μm to about 2.0 μm and a length in the second direction, Y direction, from about 100 μM to about 8000 μm. The preferable material for the first dielectric layer 401 is silicon oxide (SiO2) or silicon nitride (Si3N4).