At block 210 of FIG. 2, a semiconductor substrate containing a hard mask layer is provided. Referring to FIGS. 3A and 3B, a hard mask layer 200 may be formed on top of a semiconductor substrate 100 at a first direction, X direction, and may extend in a second direction, Y direction, with a height in the third direction, Z direction, perpendicular to the first and second directions. The semiconductor substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, a silicon on insulator (SOI) substrate, or any other commonly used semiconductor substrate. The semiconductor substrate 100 may include one or more semiconductor layers or structures and may include active or operable portions of semiconductor devices. The hard mask layer 200 may include silicon oxide (SiO₂), silicon nitride (Si₃N₄), boron nitride (BN), metal, metal nitride, and/or metal oxide and may have a thickness, the height, in a range from about 10 nm to about 100 nm. The hard mask layer 200 may have a width in the first direction, X direction, from about 0.5 μm to about 2.0 μm and a length in the second direction, Y direction, from about 100 to about 8000 μm. The hard mask layer 200 may be formed on the semiconductor substrate 100 with various deposition processes include, but are not limited to: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemical deposition (ECD), electroplating, electroless plating and spin coating. The preferable method is PVD, such as sputtering, or CVD.