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Laterally grown edge emitting laser

專利號
US10096975B1
公開日期
2018-10-09
申請人
INTERNATIONAL BUSINESS MACHINES CORPORATION(US NY Armonk)
發(fā)明人
Effendi Leobandung; Ning Li
IPC分類
H01S5/343; H01S5/30; H01S5/02
技術(shù)領(lǐng)域
layer,iii,doped,cladding,optical,dielectric,may,substrate,structure,silicon
地域: NY NY Armonk

摘要

A laterally grown edge emitting laser is provided. A semiconductor structure is disposed on a substrate. A first, a second and a third III-V optical layers are sequentially and laterally grown on and from a sidewall of the semiconductor structure. A cladding semiconductor layer is disposed next to the third III-V optical layer and electrically connected to the III-V optical layer. Then, a first contact structure and a second contact structure is disposed on and electrically connected to the semiconductor structure and the cladding semiconductor layer, respectively. In the edge emitting laser, each of the first, second and third III-V optical layers may independently include a III-V semiconductor including at least one of group III elements of boron (B), gallium (Ga), aluminum (Al) and indium (In), and at least one of group V elements of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi). The laterally grown edge emitting laser may be integrated with a metal-oxide-semiconductor field-effect transistor (MOSFET). A method for manufacturing the laterally grown edge emitting laser is also provided.

說明書

At block 220 of FIG. 2, the semiconductor substrate 100 may be etched to form a semiconductor structure. Referring to FIGS. 4A and 4B, the semiconductor substrate 100 may be etched using the hard mask layer as an etching mask to form a semiconductor structure 301 protruding above the semiconductor substrate 100 in the third direction, Z direction, perpendicular to the first and second directions. The semiconductor structure 301 may be etched to a depth of about 0.5 μm to about 2.0 μm. The semiconductor structure 301 may have a shape in the X-Y plane similar to that of the hard mask layer 200, and may have a width in the first direction, X direction, from about 0.5 μm to about 2.0 μm and a length in the second direction, Y direction, from about 100 μm to about 8000 μM. The etch process used for forming the semiconductor structure 301 may be any conventional reactive ion etching (RIE) processes using different etchants to etch the semiconductor substrate 100. The etchant or etchants may contain fluorine. In a preferred embodiment, the semiconductor substrate 301 is a silicon substrate. Many etchants may be used to etch the silicon substrate. For example, an HBr dry etch may be used to remove silicon of the semiconductor substrate 100 selective to the hard mask materials of the hard mask layer 200. The silicon etch process may also use etchants such as: Cl2/HBr/CF4/O2, and/or HBr/O2. Wet etch process may also be used in etching the semiconductor substrate 100. For example, strong alkaline substance such as aqueous KOH or TMAH solution may be used to etch silicon substrate. Since the bonding energy of Si atoms is different for each crystal plane, the etch rate by KOH or TMAH solution may be different at each crystal plane. Thus, the Si etch by KOH or TMAH solution may be highly anisotropic. In an example embodiment of the present invention, the semiconductor substrate 100 may be wet etched by KOH or TMAH solution on the Si (110) crystal plane of the semiconductor substrate 100 to form the semiconductor structure 301 with sidewalls at Si (111) crystal plane. The preferable etch method is wet etch with TMAH solution.

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