At block 260 of FIG. 2, p-doped cladding semiconductor layers may be formed and directly connected to exposed sidewalls of the third III-V optical layers 503. Referring to FIGS. 6A and 6B, p-doped cladding semiconductor layers 302 may be formed and directly connected to exposed sidewalls of the third III-V optical layers 503, and may extend in the second direction, Y direction. The p-doped cladding semiconductor layer 302 may include a p-doped semiconductor material, for example, Si doped with boron (B), aluminum (Al), gallium (Ga) and indium (In), and the p-doped semiconductor may be heavily doped such as, for example, p+-Si. The p-doped cladding semiconductor layer 302 may include a p-doped amorphous Si. A width of the p-doped cladding semiconductor layer 302 in the first direction, X direction, may be from about 0.5 μm to about 2 μm, and a length of the p-doped cladding semiconductor layer 302 in the second direction, Y direction, may be from about 100 μm to about 8000 μm. Various methods may be used to deposit the p-doped cladding semiconductor layers 302. An amorphous silicon film is usually deposited by chemical vapor deposition (CVD) such as plasma enhanced CVD (PECVD). The formation of the p-doped cladding semiconductor layers 302 may include the following steps: depositing an amorphous p-doped silicon cladding layer on the semiconductor substrate 100, for example, by PECVD; planarizing the amorphous p-doped silicon cladding layer to expose the hard mask layer 200, for example, by chemical mechanical polishing (CMP); etching back to expose the first, second, and third III-V optical layers, for example, by reactive ion etching (RIE); and patterning the amorphous p-doped silicon cladding layer to form the p-doped cladding semiconductor layer, for example, through a photolithographic process and an etching process. The amorphous silicon may be etched by RIE with etchants such as: Cl₂/HBr/CF₄/O₂, and/or HBr/O₂. The sequence of the steps as described above is preferred. However, the invention is not limited to the performance of these steps with the sequence or order presented above. In an example embodiment of the present invention, during the planarization of the amorphous p-doped silicon, the hard mask layer 200 may be removed to expose the top surface of the semiconductor structure 301 and the top surfaces of the first, second and third III-V optical layers. In this case, no etching back process may be used after the planarization process and before the patterning process.