At block 270 of FIG. 270, a second dielectric layer may be formed to cover the above described layers and structure. Referring to FIGS. 7A and 7B, a second dielectric layer 402 may be formed to cover the first dielectric layer 401, the hard mask layer 200, the semiconductor structure 301, the p-doped cladding semiconductor layer 302, and the first, second and third III-V optical layers 501, 502 and 503. In FIG. 7B, the layers under the second dielectric layer 402 are shown for the purpose of providing better understanding of the structure of the edge emitting laser. The second dielectric layer 402 may include tetraethyl orthosilicate (TEOS), silicon nitride (Si₃N₄), silicon oxide (SiO₂), silicon oxynitride (SiON), nanoporous silica, hydrogensilsesquioxanes (HSQ), Teflon-AF (polytetrafluorethylene or PTFE), silicon oxyfluoride (FSG), carbon doped SiO₂ (SiCO), hydrogenated silicon oxycarbide (SiCOH), or other low k dielectric materials. The first and second dielectric layers 401 and 402 may be formed of the same material and may be integrated to form one dielectric layer to seal the edge emitting laser. The second dielectric layer 402 may be formed with various deposition processes include, but are not limited to: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and spin coating. The preferable method is PVD, such as sputtering, or CVD. The formation of the second dielectric layer 402 may also include a planarization process, for example, chemical mechanical polishing (CMP) process to form flat top surface after the deposition process.