Voltage control utilizing multiple PWM patterns
摘要
說明書
In similar embodiments, the oversampling control period may be the same as the measurement period. Further, the measurement cycles and the oversampling control cycles may be in phase, such that they begin and end at the same times. The steady-state control cycles may also be timed such that the start and end time of each steady-state control cycle begins and ends at the same time as the beginning and ending of a oversampling control cycle, a measurement cycle, or both. In other words, the steady state control cycle could be considered to be in phase with a hypothetical multiple of the oversampling control cycle, the measurement cycle, or both. For example, if the steady-state control period were 4 times as long as the oversampling control period, the steady-state control cycle could be considered to be in phase with four coinciding oversampling control cycles.
Controlling the voltage according to the oversampling cyclic control pattern in block 108 may enable the voltage controller to react sooner to a high-transient-voltage situation. For example, if the oversampling control frequency is 10 times as fast as the steady-state control frequency, the voltage controller may be able to issue a control command to address the potentially dangerous voltage change up to 10 times as soon as it would be able to if controlling according to the steady-state cyclic control pattern.
