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Voltage control utilizing multiple PWM patterns

專利號(hào)
US10097090B1
公開日期
2018-10-09
申請(qǐng)人
International Business Machines Corporation(US NY Armonk)
發(fā)明人
Andrew Ferencz; Todd E. Takken; Paul W. Coteus; Xin Zhang
IPC分類
G05F1/00; H02M3/158; H02M1/36; H02P9/30; H02M1/08; H02M1/00
技術(shù)領(lǐng)域
voltage,steady,controller,converter,pwm,may,cyclic,pattern,in,cycle
地域: NY NY Armonk

摘要

A power-delivery system may comprise a load device and a direct-current converter configured to deliver current to the load device when the direct-current converter is in an on state. The power-deliver system may comprise a voltage-measurement system configured to measure, at a beginning of each measurement cycle in a cyclic measurement pattern, a voltage at the load device. The power-deliver system may comprise a power controller configure to receive, at the beginning of each measurement cycle, the measurement of the voltage, and to perform, at the beginning of a control cycle in a cyclic control pattern, a voltage-control decision in response to a change in the measurement of the voltage being below a voltage-change threshold. The voltage-control decision may comprise whether to switch the state of the first direct-current converter. The cyclic control pattern may operate at a first frequency, and the measurement pattern may operate at a second frequency.

說(shuō)明書

Pattern 204 represents the steady-state cyclic PWM pattern (referred to with respect to FIGS. 2A and 2B as the steady-state pattern). As disclosed by FIG. 2A, the period of the steady-state pattern is twice as long as the period of the oversampling pattern. For example, both the oversampling pattern and the steady-state pattern begin at time 206. However, whereas the first cycle of the oversampling pattern completes at time 208, the first cycle of the steady-state pattern is only halfway done at time 208, and completes at 210. Thus, in this embodiment, the frequency of the oversampling pattern is twice that of the steady-state pattern (i.e., the period of the oversampling pattern is half that of the steady-state pattern). Thus, when controlling voltage according to the steady-state pattern, the voltage controller could issue control commands at any of times 206, 210, and 214, but not, in this example, at either of times 208 or 212. Note, however, that in other embodiments, the ratio of oversampling control frequency and the steady-state control frequency may be different than 2:1. Indeed, it may be beneficial to operate an oversampling control frequency that is as high as system constraints allow. In these embodiments, the ratio of the oversampling control frequency to the steady-state control frequency may be very large (e.g., 20:1). In some such embodiments, the oversampling control frequency may be set by a required control-loop bandwidth. The control-loop bandwidth is an ability to respond to a change of a given rate. For example, if certain rates of change of voltage are expected, or if rates of change of voltage greater that a particular magnitude would be likely to result in unacceptable damage to or failure of a load device, it may be beneficial to ensure that the system is capable of reacting fast enough to respond to voltage changes of those rates. This ability may be referred to as the control-loop bandwidth. The control-loop bandwidth increases as the measurement and control frequencies increase. Thus, in some embodiments the ratio of the oversampling control frequency and the steady-state frequency may be dependent on the required control-loop bandwidth.

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