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Voltage control utilizing multiple PWM patterns

專利號
US10097090B1
公開日期
2018-10-09
申請人
International Business Machines Corporation（US NY Armonk）
發(fā)明人
Andrew Ferencz; Todd E. Takken; Paul W. Coteus; Xin Zhang
IPC分類
G05F1/00; H02M3/158; H02M1/36; H02P9/30; H02M1/08; H02M1/00
技術(shù)領(lǐng)域
voltage,steady,controller,converter,pwm,may,cyclic,pattern,in,cycle
地域： NY NY Armonk

摘要

A power-delivery system may comprise a load device and a direct-current converter configured to deliver current to the load device when the direct-current converter is in an on state. The power-deliver system may comprise a voltage-measurement system configured to measure, at a beginning of each measurement cycle in a cyclic measurement pattern, a voltage at the load device. The power-deliver system may comprise a power controller configure to receive, at the beginning of each measurement cycle, the measurement of the voltage, and to perform, at the beginning of a control cycle in a cyclic control pattern, a voltage-control decision in response to a change in the measurement of the voltage being below a voltage-change threshold. The voltage-control decision may comprise whether to switch the state of the first direct-current converter. The cyclic control pattern may operate at a first frequency, and the measurement pattern may operate at a second frequency.

說明書

FIG. 7 depicts the representative major components of an exemplary Computer System 701 that may be used in accordance with embodiments of the present disclosure. The particular components depicted are presented for the purpose of example only and are not necessarily the only such variations. The Computer System 701 may comprise a Processor 710, Memory 720, an Input/Output Interface (also referred to herein as I/O or I/O Interface) 730, and a Main Bus 740. The Main Bus 740 may provide communication pathways for the other components of the Computer System 701. In some embodiments, the Main Bus 740 may connect to other components such as a specialized digital signal processor (not depicted).

The Processor 710 of the Computer System 701 may be comprised of one or more CPUs 712. The Processor 710 may additionally be comprised of one or more memory buffers or caches (not depicted) that provide temporary storage of instructions and data for the CPU 712. The CPU 712 may perform instructions on input provided from the caches or from the Memory 720 and output the result to caches or the Memory 720. The CPU 712 may be comprised of one or more circuits configured to perform one or methods consistent with embodiments of the present disclosure. In some embodiments, the Computer System 701 may contain multiple Processors 710 typical of a relatively large system. In other embodiments, however, the Computer System 701 may be a single processor with a singular CPU 712.

權(quán)利要求

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